By Frank Oppenheimer, Julio Luis Medina Pasaje

This booklet brings jointly a variety of the simplest papers from the 17th variation of the discussion board on specification and layout Languages convention (FDL), which happened on October 14-16, 2014, in Munich, Germany. FDL is a well-established overseas discussion board dedicated to dissemination of study effects, functional stories and new principles within the program of specification, layout and verification languages to the layout, modeling and verification of built-in circuits, complicated hardware/software embedded structures, and mixed-technology systems.

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Fault injection by mutations needs initial manual manipulation of the nominal model of a component, however saboteurs may act at the signal interfaces of the hardware (HW) component. g. stuck-at, single event upset, bit-flip), in the analogue domain so far no broadly exercised fault models were established which is due to a greater variety of fault manifestations as a failure mode (continuous signal values) and greater simulation expenses [18]. Therefore different approaches have been proposed in order to enhance efficiency of fault simulations.

For automatic implementation of saboteurs into the item model, a design automation script in SKILL language is written which is executable within the Cadence Virtuoso environment. The design automation procedure requires three parameters, defining directory paths of the initial test-bench (mixed HDL and spice), of the fault model library and injection directive are passed to the main procedure. First the initial test-bench, comprising the selected components, is duplicated. Then the 32 Fig. 3 Concept of fault injection automation O.

The presented work comprises a constitutive approach and can be used for further investigations of simulation-based single-point/residual and multiple-point analogue fault injection in order to support evaluation of safety goal violations due to random hardware faults, in accordance with the ISO 26262. Furthermore, it allows a differentiated argumentation in the context of random hardware fault classification, by accounting for additional factors which contribute to the failure severity. Further investigation is needed in order to support plausibility analyses for multiple-point faults and elaboration of diagnostic coverage of safety mechanisms.

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