By Guangyu Sun

This ebook equips readers with instruments for laptop structure of excessive functionality, low energy, and excessive reliability reminiscence hierarchy in computers in accordance with rising reminiscence applied sciences, comparable to STTRAM, PCM, FBDRAM, and so forth. The options defined supply benefits of excessive density, near-zero static energy, and immunity to delicate error, that have the possibility of overcoming the “memory wall.” The authors speak about reminiscence layout from quite a few views: rising reminiscence applied sciences are hired within the reminiscence hierarchy with novel structure amendment; hybrid reminiscence constitution is brought to leverage merits from a number of reminiscence applied sciences; an analytical version named “Moguls” is brought to discover quantitatively the optimization layout of a reminiscence hierarchy; eventually, the vulnerability of the CMPs to radiation-based delicate error is more advantageous by means of exchanging diverse degrees of on-chip reminiscence with STT-RAMs.

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As shown in Fig. 24, the access to each data block is in parallel so that the impact on performance is minimized. Consequently, the number of duplicated peripheral circuitry equals to the number of data block in a PRAM memory line, which is decided by FV length. FV number also has an impact on performance of the memory architecture. Apparently, a higher FV-ratio can be achieved with a larger FV table because more frequent values can be identified. However, the capacities of FV table and CAM are increased with the FV number.

The size of log pages in an erase unit is limited, and these log sectors themselves do not allow in-place updating. This may cause significant performance degradation for some cases. Particularly, if there are frequent updates to the same erase unit, it would quickly run out its log sectors and cause merge operations frequently. Moreover, if there are multiple updates to the same data, only the latest updated one is valid. Consequently, the effective log sector capacity of an erase unit becomes smaller, which would worsen the problem of the IPL approach.

Compared to the static profiling, the global incremental profiling is suitable for the case of running applications with different input data. 3 Management of Frequent Values in CMPs Prior research about frequent-value locality focuses on the architecture in a singlecore processor. As the mainstream architecture moves to the modern CMPs, the management of frequent values become more complicated. When the multi-thread/ multi-programmed applications are executed on CMPs, the management of frequent values should be managed carefully to make sure that accesses to frequent values are correct.

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