By K. Sridharan, Vikramkumar Pudi

This learn monograph specializes in the layout of mathematics circuits in Quantum Dot mobile Automata (QCA). utilizing the truth that the 3-input majority gate is a primitive in QCA, the ebook units out to find hitherto unknown homes of majority common sense within the context of mathematics circuit designs.

The pursuit for effective adders in QCA takes types. One contains software of the hot leads to majority common sense to current adders. the second one comprises improvement of a customized adder for QCA know-how. A QCA adder named as hybrid adder is proposed and it truly is proven that it outperforms current multi-bit adders with appreciate to zone and hold up. The paintings is prolonged to the layout of a low-complexity multiplier for signed numbers in QCA. in addition the booklet explores facets targeted to QCA know-how, specifically thermal robustness and the function of interconnects.

In addition, the booklet introduces the reader to QCA structure layout and simulation utilizing QCADesigner.

Features & Benefits:

This research-based book:

·Introduces the reader to Quantum Dot mobile Automata, an rising nanotechnology.

·Explores houses of majority logic.

·Demonstrates software of the houses to layout effective mathematics circuits.

·Guides the reader in the direction of format layout and simulation in QCADesigner.

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Extra resources for Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology

Sample text

N4 + n4 = n2 ). So total reduction of majority gates, denoted by Ir (n), is sum of reduction of majority gates from carry n2 + 1 to n (denoted by Ir (n : n2 +1)) and reduction of majority gates from carry n2 to 1 (denoted by Ir ( n2 )). Ir (n) = Ir n : n2 + 1 + Ir n2 = n2 + Ir n2 = n2 + n4 + · · · + 4 + 2 + Ir (2) = n−2+1 [Ir (2) = 1] = n−1 46 4 Design of Ripple Carry and Prefix Adders in QCA Therefore, Ic (n) = Icd (n) − Ir (n) = 4n − 3 log2 (n) − 4 For an n-bit adder, gi and pi require one majority gate each, hence Ig p (n) = 2n majority gates.

1. 0. In general, layout design also involves specifying appropriate clock zones. In this case, all the cells are set to Clock 0. The complexity of the QCA design depicted in Fig. 1 can be expressed by the cell count, area as well as delay. An outline of the procedure for calculating cell count and other parameters is provided in the Appendix. The results of simulation of a 2-input OR gate in QCADesigner are shown in Fig. 2. It can be observed that the output is the OR of the two input values. ) Similarly, the AND of two inputs, A and B, is realized as M(A, B, 0).

We can use the result on a 1-bit full adder to derive the following for an n-bit RCA. 5 An n-bit RCA requires at most 3n majority gates and n inverters. 5, we see that a 4-bit RCA requires 12 majority gates and 4 inverters. 1 Design of the Ripple Carry Adder (RCA) in QCA 31 A3 B3 A2 B2 A1 B1 A0 B0 Cin D0 D0 D0 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 D1 M D1 D2 D2 D2 D2 M D2 D3 D3 D1 D1 D1 M D3 D2 M D2 D2 M D2 D3 D2 D2 M D3 D3 M D3 D0 D0 D0 D3 D3 M D0 D3 M D0 D0 D0 M D0 D0 M D1 D1 D1 D1 D1 D1 D1 M D2 D2 D2 D2 D2 Cout S3 S2 S1 S0 Fig.

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